Verilog HDL Code for All Logic Gates

This page provides Verilog HDL code for implementing all common logic gates. Below, you’ll find the Verilog code along with a reference to a truth table image for clarity.

Image alt: all gates truth table with symbol

Verilog Code

Here’s the Verilog code for a module that implements AND, OR, NOT, NAND, NOR, and XOR gates:

module allgate ( a, b, y );
  input a, b;
  output [1:6] y;

  assign y[1] = a & b;  // AND
  assign y[2] = a | b;  // OR
  assign y[3] = ~a;     // NOT
  assign y[4] = ~(a & b); // NAND
  assign y[5] = ~(a | b); // NOR
  assign y[6] = a ^ b;  // XOR
endmodule

Simulation and Verification

To verify the functionality of the code, follow these steps:

1. After the program is synthesized, create a Test Bench (TBW) file to apply inputs to the module.
2. Highlight the TBW file.
3. Use Modelsim to simulate the behavioral model. This step allows you to observe the outputs for given inputs.
4. Examine the waveform to view the simulation results. Zoom in on the waveform for a detailed view of the logic gate outputs.

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