Verilog Code for Binary Up/Down Counter
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This article provides Verilog HDL code for a binary up/down counter.
Symbol and Truth Table
The following is the truth table of the binary up/down counter:
| Clk | Rst | Dir | Qout |
|---|---|---|---|
| X | 1 | X | 0000 |
| 1 | 0 | 0 | 0001 |
| 1 | 0 | 0 | 0010 |
| 1 | 0 | 0 | 0011 |
| 1 | 0 | 0 | 0100 |
| 1 | 0 | 0 | 0101 |
| 1 | 0 | 0 | 0110 |
| 1 | 0 | 0 | 0111 |
| 1 | 0 | 0 | 1000 |
| 1 | 0 | 0 | 1001 |
| 1 | 0 | 0 | 1010 |
| 1 | 0 | 0 | 1011 |
| 1 | 0 | 0 | 1100 |
| 1 | 0 | 0 | 1101 |
| 1 | 0 | 0 | 1110 |
| 1 | 0 | 0 | 1111 |
Verilog Code
module bin_as(clk,clr,dir, temp);
input clk,clr,dir;
output reg[3:0] temp;
always@(posedge clk,posedge clr)
begin
if(clr==0)
begin
if(dir==0)
temp=temp+1;
else
temp=temp-1;
end
else
temp=4'd0;
end
endmoduleSimulation Result
Here’s the simulation result of the above Verilog code:
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