Full Adder Verilog HDL Code

This page provides the Verilog HDL code for a full adder.

Image alt: Full Adder Symbol

Truth Table

The truth table below illustrates the behavior of a full adder:

Input-a	Input-b	Input-cin	Output-SUM	Output-Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Full Adder Verilog Code

module fulladder (
    input a, b, c,
    output s, cout
);

    assign s = a ^ b ^ c;
    assign cout = (a & b) | (a & c) | (b & c); // Corrected Cout assignment
endmodule

Explanation:

• The module fulladder takes three inputs: a, b, and c (carry-in).
• It produces two outputs: s (sum) and cout (carry-out).
• The assign statements define the combinational logic.
• The sum s is calculated as the XOR of the three inputs.
• The carry-out cout is (a & b) | (a & c) | (b & c). This is corrected for a standard Cout assignment.

Simulation Result

Image alt: Full Adder Simulation Result

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