4-Bit BCD Synchronous Reset Counter Verilog Code

This article provides Verilog source code for a 4 Bit BCD Synchronous Reset Counter. You’ll also find the block diagram and truth table to help understand its operation.

Block Diagram and Truth Table

Here’s a look at the block diagram and truth table for the 4 Bit BCD Synchronous Reset Counter:

4 Bit BCD Synchronous Reset Counter Block Diagram

4 Bit BCD Synchronous Reset Counter Truth Table

4 Bit BCD Synchronous Reset Counter Verilog Code

module bin_sync( clk, rst, bcd_out);
    input clk, rst;
    output [3:0] bcd_out;
    reg [3:0] bcd_out;
    reg [22:0] div;
    reg clkdiv;

    initial begin
        bcd_out = 4'd0;
        div = 23'd0;
        clkdiv = 1'b0;
    end

    always @ (posedge clk) begin
        div <= div + 1'b1;
        clkdiv <= div[22];
    end

    always @ (posedge clkdiv) begin
        if (rst)
            bcd_out <= 4'd0;
        else if(bcd_out < 4'd9)
            bcd_out <= bcd_out + 4'd1;
        else
            bcd_out <= 4'd0;
    end

endmodule

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