PRBS Generator Verilog Code and Test Bench

This page provides the Verilog code for a PRBS (Pseudo-Random Binary Sequence) generator and a corresponding test bench script.

PRBS Generator Verilog Code

The following is the Verilog code for a PRBS generator:

module prbs (rand, clk, reset);
  input clk, reset;
  output rand;
  wire rand;
  reg [3:0] temp;

  always @ (posedge reset) begin
    temp <= 4'hf;
  end

  always @ (posedge clk) begin
    if (~reset) begin
      temp <= {temp[0]^temp[1],temp[3],temp[2],temp[1]};
    end
  end

  assign rand = temp[0];

endmodule

Explanation:

• The module prbs has inputs clk (clock) and reset, and an output rand (random bit).
• temp is a 4-bit register that holds the state of the PRBS generator.
• The always @ (posedge reset) block initializes the temp register to 4'hf (1111 in binary) when the reset signal is asserted (positive edge).
• The always @ (posedge clk) block updates the temp register on each rising edge of the clock.
• The core logic of the PRBS generator is within the if (~reset) statement. It implements a linear feedback shift register (LFSR) with a specific feedback tap. The next state of temp is derived by XORing temp[0] and temp[1] and shifting the bits.
• The assign rand = temp[0] statement assigns the value of the least significant bit of temp to the output rand. This provides the pseudo-random bit.

PRBS Generator Test Script Code

Here’s the test script code for the PRBS generator:

module main;
  reg clk, reset;
  wire rand;

  prbs pr (rand, clk, reset);

  initial begin
    forever begin
      clk <= 0;
      #5 clk <= 1;
      #5 clk <= 0;
    end
  end

  initial begin
    reset = 1;
    #12 reset = 0;
    #90 reset = 1;
    #12 reset = 0;
  end

endmodule

Explanation:

• The main module instantiates the prbs module.
• clk and reset are declared as reg because their values are driven by the test bench. rand is a wire because it’s an output from the prbs module.
• The first initial block generates a clock signal with a period of 10 time units (5 for the low phase and 5 for the high phase).
• The second initial block generates a reset signal. It asserts the reset for 12 time units, de-asserts it for 90 time units, asserts it again for 12 time units, and then de-asserts it again. This provides a couple of reset cycles for testing the PRBS generator.

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