Shift Left Shift Right Register Verilog Code and Test Bench

This document provides Verilog code for a Shift Left Shift Right Register, along with a corresponding test bench.

Shift Left Shift Right Register Verilog Code

The following is the Verilog code for a Shift Left Shift Right Register.

module slsr(sl, sr, din, clk, reset, Q);
  input sl, sr, din, clk, reset;
  output [7:0] Q;
  reg [7:0] Q;

  always @ (posedge clk)
  begin
    if (~reset)
    begin
      if (sl)
      begin
        Q <= #2 {Q[6:0],din};
      end
      else if (sr)
      begin
        Q <= #2 {din, Q[7:1]};
      end
    end
  end

  always @ (posedge reset)
  begin
    Q<= 8'b00000000;
  end

endmodule

Explanation:

• Module Declaration: module slsr(sl, sr, din, clk, reset, Q); defines the module named slsr with its input and output ports.
• Inputs:
  • sl: Shift Left enable signal.
  • sr: Shift Right enable signal.
  • din: Data input.
  • clk: Clock signal.
  • reset: Reset signal.
• Output:
  • Q: 8-bit output register.
• Register Declaration: reg [7:0] Q; declares an 8-bit register named Q.
• Clocked Always Block: always @ (posedge clk) defines a sequential block triggered on the positive edge of the clock signal.
• Reset Condition: if (~reset) checks if the reset signal is inactive (low).
• Shift Left Condition: if (sl) checks if the shift left enable is active. If so, the register Q is updated by shifting its contents one bit to the left and inserting the value of din into the least significant bit (LSB). Q <= #2 {Q[6:0],din}; implements this with a delay of 2 time units.
• Shift Right Condition: else if (sr) checks if the shift right enable is active. If so, the register Q is updated by shifting its contents one bit to the right and inserting the value of din into the most significant bit (MSB). Q <= #2 {din, Q[7:1]}; implements this with a delay of 2 time units.
• Reset Always Block: always @ (posedge reset) defines a sequential block triggered on the positive edge of the reset signal.
• Reset Action: Q<= 8'b00000000; sets the register Q to all zeros when the reset signal is active (high).

Shift Left Shift Right Register Test Bench Code

The following is the test bench code for the Shift Left Shift Right Register.

module main;
  reg clk, reset, din, sl, sr;
  wire [7:0] q;

  slsr slsr1(sl, sr, din, clk, reset, q);

  initial
  begin
    forever
    begin
      clk <= 0;
      #5 clk <= 1;
      #5 clk <= 0;
    end
  end

  initial
  begin
    reset = 1;
    #12 reset = 0;
    #90 reset = 1;
    #12 reset = 0;
  end

  initial
  begin
    sl = 1;
    sr = 0;
    #50 sl = 0;
    #12 sr = 1;
  end

  initial
  begin
    forever
    begin
      din = 0;
      #7 din = 1;
      #8 din = 0;
    end
  end

endmodule

Explanation:

• Module Declaration: module main; defines the test bench module named main.
• Signal Declarations:
  • reg clk, reset, din, sl, sr; declares the input signals as registers.
  • wire [7:0] q; declares the output signal from the module under test as a wire.
• Instantiation: slsr slsr1(sl, sr, din, clk, reset, q); instantiates the slsr module.
• Clock Generation: The first initial block generates a clock signal with a period of 10 time units (5 for low and 5 for high).
• Reset Generation: The second initial block generates a reset signal, initially high for 12 time units, then low for 90 time units, then high again for 12 time units, and finally low.
• Shift Enable Generation: The third initial block sets sl high and sr low for 50 time units, then sets sl low and sr high for 12 time units.
• Data Input Generation: The fourth initial block generates a repeating pattern for the data input din.