
1-Bit and 4-Bit Comparator Design in Verilog
This article presents Verilog HDL code for designing 1-bit and 4-bit comparators, including truth tables and simulation results.
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This article presents Verilog HDL code for designing 1-bit and 4-bit comparators, including truth tables and simulation results.
Verilog HDL code for a 2 to 4 decoder implementation, truth table, and simulation results.
Verilog source code for a 32-bit Arithmetic Logic Unit (ALU) capable of performing arithmetic and logical operations. Includes truth table and simulation results.
Verilog code for a 4-bit BCD asynchronous reset counter, including module definition and reset functionality.
Verilog source code for a 4-bit BCD synchronous reset counter, block diagram, and truth table for understanding its operation.
Verilog code implementation of a 4-bit binary asynchronous reset counter, including block diagram and truth table.
Verilog code for a 4-bit binary synchronous reset counter, complete with a block diagram and truth table for understanding its operation.
Verilog implementation of a 4-bit binary to Gray code counter converter with symbol, truth table, and simulation results.
Verilog code for a 4-bit down counter is presented, along with its corresponding test bench for simulation and verification.
Verilog code for a 4-bit Mod 13 counter with its test bench, including explanations of the code's functionality.
Verilog HDL code for a 4-to-1 multiplexer and a 1-to-4 demultiplexer, including truth tables and simulation results.
Verilog HDL code for an 8-to-1 multiplexer, including its symbol, truth table, and simulation results.
Verilog source code for an 8-to-3 encoder without priority, including a block diagram and truth table for understanding its functionality.
Verilog code for an 8-to-3 priority encoder, including the truth table, schematic, code explanation, and simulation results.
Verilog code for an 8-to-3 priority encoder, complete with a block diagram and truth table for understanding its functionality.
Verilog code implementation of an Asynchronous FIFO, including a test bench and simulation output analysis.
Explore a D flip-flop implementation without reset, including Verilog code, test bench, simulation results, and RTL schematic.
Explore the Verilog code, test bench, simulation, and RTL schematic of a D flip-flop with synchronous reset.
Verilog HDL implementation of a full adder, including truth table, code, and simulation results.
This article presents a Verilog implementation of a low-pass FIR filter using coefficients generated from MATLAB and converted to Q-15 format.
Explore Verilog implementations of Mealy and Moore state machines, highlighting the differences in their output logic.
Verilog code and test bench for a parallel load shift left register, including explanations of the code's functionality.
Verilog code for a PRBS generator and its test bench are presented, explaining the linear feedback shift register (LFSR) implementation.
Explore Verilog code implementations for RAM (Random Access Memory) and ROM (Read Only Memory) with detailed examples and figures.
Verilog code and test bench for a Shift Left Shift Right Register. Includes module declaration, reset, shift conditions, and explanation.
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