QPSK Modulation/Demodulation VHDL Source Code

This page provides VHDL source code for QPSK modulation and demodulation.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- entity declaration
entity qpsk_mod_n is
    Port (
        clk                  : in  std_logic;  -- global clock
        valid_in             : in  std_logic;  -- when high din is valid
        data_in              : in  std_logic_vector(1 downto 0);  -- data in
        reset                : in  std_logic;  -- asynchronous active high reset
        valid_out            : out std_logic;  -- when high real and imag is valid
        dout_real, dout_imag : out std_logic_vector(15 downto 0)  -- real and imag out
    );
end qpsk_mod_n;

-- architecture declaration
architecture Behavioral of qpsk_mod_n is
    signal sig_valid_out   :     std_logic;
    signal valid_out1      :     std_logic;
    signal sig_valid_out1  :     std_logic;
begin
    -- process to map QPSK constellation
    process(clk, reset)
    begin
        if(reset = '1') then
            dout_real      <= x"0000";
            dout_imag      <= x"0000";
            valid_out1     <= '0';
            sig_valid_out  <= '0';
            sig_valid_out1 <= '0';
        elsif(clk = '1' and clk'event) then
            valid_out1     <= '1';
            sig_valid_out  <= valid_out1;
            sig_valid_out1 <= sig_valid_out;

            if valid_in = '1' then
                case data_in is
                    when "00"   =>
                        dout_imag  <= x"2d41";
                        dout_real  <= x"2d41";
                        valid_out1 <= '1';  -- Based on the input data assign
                    when "01"   =>
                        dout_imag  <= x"D2BF";  -- values to the output ports
                        dout_real  <= x"2d41";
                        valid_out1 <= '1';
                    when "10"   =>
                        dout_imag  <= x"2d41";
                        dout_real  <= x"D2BF";
                        valid_out1 <= '1';
                    when "11"   =>
                        dout_imag  <= x"D2BF";
                        dout_real  <= x"D2BF";
                        valid_out1 <= '1';
                    when others =>
                        dout_imag  <= x"D2BF";
                        dout_real  <= x"D2BF";
                        valid_out1 <= '1';
                end case;
            else
                dout_imag  <= x"0000";
                dout_real  <= x"0000";
                valid_out1 <= '0';
            end if;
        end if;
    end process;

    valid_out                         <= valid_out1;

end behavioral;

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