4 bit mod 13 counter verilog code | 4 bit mod 13 counter test bench

This page covers 4 bit mod 13 counter verilog code and 4 bit mod 13 counter test bench code script.

4 bit mod 13 counter verilog code | 4 bit mod 13 counter test bench

Following is the verilog code of 4 bit mod 13 counter.

'define TICK #2 

module mod13Cntr(clk, reset, Q);

input clk, reset;

output [3:0] Q;

reg [3:0] Q;



//Behavioral Code for a Mod-13 counter

always @ (posedge clk) begin

if (~reset) begin

if (Q == 4'b1100) begin

Q <= 'TICK 4'b0;

end

else begin

Q <= 'TICK Q+1;

end

end

end



always @ (posedge reset) begin

Q <= 4'b0000;

end



endmodule

4 bit mod 13 counter test bench

Following is the test bench code of 4 bit mod 13 counter.

module main; 

reg clk, reset; 

wire [3:0] Q; 

downCntr dnCntr1(clk, reset, Q); 



initial begin 

forever begin 

clk <= 0;

#5

clk <= 1;

#5

clk <= 0;

end

end



initial begin

reset = 1;

#12

reset = 0;

#170

reset = 1;

#12

reset = 0;

end

endmodule

Verilog source codes

Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates

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