4 bit down counter verilog code | 4 bit down counter test bench code

This page covers 4 bit down counter verilog code and 4 bit down counter test bench code.

4 bit down counter verilog code

Following is the 4 bit down counter verilog code.

'define TICK #2 

module downCntr(clk, reset, Q);

input clk, reset;

output [3:0] Q;

reg [3:0] Q;



//Behavioral Code for a Down Counter

always @ (posedge clk) begin

if (~reset) begin

Q <= 'TICK Q-1;

end

end



always @ (posedge reset) begin

Q <= 4'b0000;

end



endmodule

4 bit down counter test bench code

Following is the test code script for 4 bit down counter.

module main; 

reg clk, reset; 

wire [3:0] Q; 

downCntr dnCntr1(clk, reset, Q); 



initial begin 

forever begin 

clk <= 0; 

#5 

clk <= 1; 

#5 

clk <= 0; 

end 

end 



initial begin 

reset = 1; 

#12 

reset = 0; 

#170 

reset = 1; 

#12 

reset = 0; 

end 


endmodule 

Verilog source codes

Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates

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