D Latch VHDL Source Code

By RF Wireless Expert Team

Last Updated: August 25, 2026

This page provides VHDL source code for a D Latch.

VHDL Code for D Latch

entity mydlatch1 is
    port (
        signal d, g: in std_logic;
        signal q: out std_logic
    );
end mydlatch1;

architecture behavior of mydlatch1 is
-- rising edge triggered DFF
begin
    process (g, d)
    begin
        if (g = '1') then
            q <= d;
        end if;
    end process;
end behavior;

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D Latch VHDL Source Code

VHDL Code for D Latch

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