D Flip-Flop VHDL Source Code

By RF Wireless Expert Team

Last Updated: August 25, 2026

This page provides the VHDL source code for a D Flip-Flop.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DFF1 is
    Port (
        d, res, clk : in  STD_LOGIC;
        q           : out STD_LOGIC
    );
end DFF1;

architecture Behavioral of DFF1 is
begin
    process(clk)
    begin
        if (res = '1') then
            q <= '0';
        elsif clk'event and clk = '1' then
            q <= d;
        end if;
    end process;
end behavioral;

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D Flip-Flop VHDL Source Code

VHDL Code

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