4 Bit Binary Asynchronous Reset Counter Verilog Code

This page of Verilog source code section covers 4 Bit Binary Asynchronous Reset Counter Verilog Code. The block diagram and truth table of 4 Bit Binary Asynchronous Reset Counter Verilog Code is also mentioned.

Block Diagram of 4 Bit Binary Asynchronous Reset Counter


4 bit Binary Asynchronous Reset Counter Block Diagram

Truth Table of 4 Bit Binary Asynchronous Reset Counter


4 bit Binary Asynchronous Reset Counter Truth Table

4 Bit Binary Asynchronous Reset Counter Verilog Code

module bin_sync( clk, rst, bin_out); 
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge( clkdiv))
begin
if (rst=0)
bin_out=4'b0000;
else
bin_out=bin_out+4'b0001;
end
endmodule



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