JESD204A vs JESD204B-difference between JESD204A and JESD204B

This page compares JESD204A vs JESD204B and mentions difference between JESD204A and JESD204B in tabular format.

Features JESD204A JESD204B
Interface diagrams JESD204A JESD204B
Release 2008 2011
Lane Rate (Maximum) 3.125 Gbps 12.5 Gbps
Clock Signal The frame clock signal in the system equal to frame rate of the data on the link. In JESD204A, frame clock is the master timing reference. The device clock signal in the system can be used to derive the frame rate of the data on the link. In JESD204B, the frame clock is no longer the master system reference.
SYNC A system synchronous, active low signal from the receiver to the transmitter denotes state of synchronization. Same as JESD204A, except synchronous to local multi-frame clock (LMFC) instead of frame clock.
Lane 0,....,L-1 Differential lanes on the link (typically high speed CML). 8B/10B code groups are transmitted MSB first/LSB last. Same as JESD204A
Multiple lanes Supported Supported
Lane synchronization Supported Supported
Multi-device synchronization Supported Supported
Deterministic latency Not supported Supported
Harmonic clocking Not supported supported

Refer JESD204B tutorial >> which describes protocol layer and interfaces.

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