ECL vs LVDS vs CML-Difference between ECL LVDS CML

This page compares ECL vs LVDS vs CML and mentions difference between ECL, LVDS and CML.

ECL-Emitter Coupled Logic

ECL was introduced as alternative of TTL logic family due to its high speed data transmission. This is due to the fact that transistors remain in active region always. Hence they can change the state very fast.

Following are characteristics of ECL logic family.
• propagation rate is about 1 to 2ns
• Noise immunity and power dissipation is worst of all the logic families.
• High Level is -0.8V and Low Level is -1.8V
• It has differential input amplifier, Internal temperature and voltage compensated bias network, emitter follower outputs
• ECL gates provide both true as well as complemented outputs.

There are two disadvantages of ECL as follows.
➨It requires relatively high currents.
➨It relies on negative power supply. This makes it difficult to interface with positive supply based devices on the system.
Refer Advantages and disadvantages of ECL for more information.

PECL and LVPECL are successor to ECL logic family.
Refer difference between ECL vs PECL vs LVPECL >>.

LVDS-Low Voltage Differential Signaling

• It is invented by National Semiconductor who helped in standardizing LVDS and it is published as ANSI/TIA/EIA-644-A. The other IEEE version of LVDS i.e. IEEE 1596.3 specifies lower swing and lower power alternative to ECL logic interface. TIA version of LVDS is most commonly used.
• It offers high speed and low power differential interface.
• It supports both point to point and multidrop bus configurations.
• The LVDS driver provides 350mV differential output centered at about +1.25V typically. The driver is used with 100 Ohm interconnects terminated in 100 Ohms.
• It offers data rate in range from DC to 2.5 GBps.
• The latest version of LVDS is known as M-LVDS and it is published in ANSI/TIA/EIA-899. The M-LVDS supports multipoint bus with double terminations. M-LVDS supports 500 Mbps or less data rates.
• LVDS and M-LVDS offers lower EMI (Electro-Magnetic Interference) due to small output current and equal/opposite current flow within pair.
• LVDS is very versatible and supports different bus configurations.

CML-Current Mode Logic

• CML is popular due to its simplicity and speed.
• It is high speed point to point interface.
• It does not need any external terminating resistors. This is taken care internally by driver and receiver devices.
• CML supports data rates of greater than 10 Gbps.
• It may be DC coupled or AC coupled provided encoding is used.
• XAUI SerDes implementations employ CML interface on high speed side.
• CML interface is vendor specific. It is not standardized but it meets clause 47 of IEEE 802.3 requirements.
• CML mainly employs point to point bus configuration mode.

Following table mentions difference between ECL, LVDS and CML logic families.

Specification	ECL	LVDS	CML
Bus structure	Point to Point, Multidrop, Multipoint	Point to Point, Multidrop, Multipoint (Supported by M-LVDS)	Point to Point
Power Dissipation	High	Low	Medium
Speed	DC to >10 Gbps	DC to >2 Gbps	DC to >10 Gbps
Coupling	DC or AC	DC	DC or AC
Process	Bipolar	CMOS, BiCMOS	Bipolar, CMOS
Output Swing	700 to 800 mV	350 mV (Smallest)	800 mV

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