SoC Basics

This article gives introduction to SoC basics,SoC execution flow. We will see what makes a SoC and steps involved in getting the chip from architecture to SoC samples.

What is SoC(System On a Chip)

An Integrated Circuit (IC) which has the system fully integrated on a single Die System. This represents a combination of general purpose processor,hardware accelerators, peripheral interfaces and storage devices.

Packaging,Connecting Die to Pins

Wire bond:
• Wires have Resistance and Inductance.
• Limitations on high frequency interfaces.
• Physical limitation on number of wires.

Flip Chip:
• Direct contact has low resistance and apprix. zero inductance
• High frequency interfaces
• Large number of interfaces
• Contacts can be in the middle of the die

SoC Execution Flow

SoC Execution Flow

Design Abstraction Levels

Lexical Coding or Behavioral Design, Functional Level- System Level, Algorithmic Level, RTL Level Netlist with Standard Cells-Gate level Typically used by Analog Designers-Transistor Level Mask output of Physical Design-Custom/Layout Level

Execution Flow Design Levels

SoC Execution flow phases

Following are the steps involved in SoC design flow.

• System level algorithm design from the specification needed.

• Register tarnsfer level(HDL coding in RTL/DFT)

• Gate level(synthesis resulting into netlist)

• Schematic level(place and route resulting into layout)

• Silicon as output of the entire process


Production tests on RF and SoC devices
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FPGA kit -FPGA evaluation kit manufacturers
VHDL Tutorial
FPGA Implementation of MIMO
Beamforming smart antenna using FPGA
WiMAX SoC Vendors

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