VHDL Code for Square Wave Generation using DAC

This article presents VHDL code designed to generate a square wave using a Digital-to-Analog Converter (DAC).

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sqwave is
    port(
        clk, rst: in std_logic;
        dac_out: out std_logic_vector(7 downto 0)
    );
end sqwave;

architecture Behavioral of sqwave is
    signal counter : std_logic_vector(7 downto 0);
    signal div: std_logic_vector(3 downto 0);
    signal clkdiv: std_logic;
begin
    process(clk)
    begin
        if (rising_edge(clk)) then
            div <= div + '1' ;
        end if;
    end process;

    clkdiv<=div(3);

    process(clkdiv)
    begin
        if (rst='1') then
            counter <= "00000000";
        elsif (rising_edge(clkdiv)) then
            counter <= counter + 1 ;
        end if;
    end process;

    process(counter) is
    begin
        if(counter<=128)then
            dac_out<="11111111";
        else
            dac_out<="00000000";
        end if;
    end process;

end Behavioral;

Explanation of the VHDL Code

This VHDL code describes an entity sqwave that outputs a square wave via the dac_out port. Let’s break down the key sections:

• Libraries: The code begins by declaring necessary IEEE libraries:

  • ieee.std_logic_1164.all: Provides the standard logic data type (std_logic).
  • ieee.std_logic_arith.all: Offers arithmetic operations for std_logic_vector.
  • ieee.std_logic_unsigned.all: Enables treating std_logic_vector as unsigned numbers.

• Entity Declaration (sqwave): Defines the interface of the module:

  • clk: Input clock signal.
  • rst: Input reset signal.
  • dac_out: Output port, an 8-bit std_logic_vector representing the DAC output.

• Architecture (Behavioral): Implements the behavior of the square wave generator:

  • Signals: Declares internal signals:
    • counter: An 8-bit counter used to determine the high/low state of the square wave.
    • div: A 4-bit prescaler for clock division.
    • clkdiv: The divided clock signal.
  • Clock Division Process: This process divides the input clock clk to generate a slower clock signal, clkdiv. The div signal acts as a counter, incrementing on each rising edge of clk. clkdiv is assigned the most significant bit of div, effectively dividing the clock frequency by 16.
  • Counter Process: This process increments the counter on each rising edge of the divided clock clkdiv, provided the reset signal rst is low. If rst is high, the counter is reset to “00000000”.
  • DAC Output Process: This process determines the value output to the dac_out port based on the value of the counter. If the counter is less than or equal to 128, the dac_out is set to “11111111” (all bits high), representing the high level of the square wave. Otherwise, dac_out is set to “00000000” (all bits low), representing the low level of the square wave.

Functional Overview

The code operates by dividing the input clock and using a counter to generate a symmetrical square wave. The prescaler slows down the counting frequency, allowing for a lower frequency square wave output compared to the input clock. The counter counts up to a threshold (128 in this case), switching the dac_out between its maximum and minimum values, creating the square wave.