VHDL Code for Basic Logic Gates

By RF Wireless Expert Team

Last Updated: August 25, 2026

This page provides VHDL source code for implementing all basic logic gates.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity gates is
    port (
        a_in, b_in: in std_logic;
        not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op: out std_logic
    );
end gates;

architecture dataflow of gates is
begin
    not_op <= not a_in;
    and_op <= a_in and b_in;
    nand_op <= a_in nand b_in;
    or_op <= a_in or b_in;
    nor_op <= a_in nor b_in;
    xor_op <= a_in xor b_in;
    xnor_op <= a_in xnor b_in;
end ;

Explore VHDL Digital Logic Gates, Mux & Encoders

Continue Learning VHDL

VHDL Language Tutorial

Keep Reading

Source-Code/VHDL
1x8 Demultiplexer VHDL Source Code
VHDL source code for a 1x8 demultiplexer (DEMUX) implementation. Includes code and related VHDL resources.
Source-Code/VHDL
4-Bit Braun Multiplier VHDL Code
VHDL source code implementation of a 4-bit Braun multiplier, commonly used in digital signal processing and computer arithmetic.
Source-Code/VHDL
4-Bit Up/Down Counter VHDL Source Code
VHDL source code for a 4-bit up/down counter with reset, load, and direction control.
Source-Code/VHDL
7-Segment Display Interface VHDL Source Code
VHDL code for interfacing with a 7-segment display, including entity declaration and architecture implementation.
Source-Code/VHDL
BCD Up/Down Counter VHDL Source Code
VHDL code examples for BCD up and down counters, including complete, synthesizable code blocks.
Source-Code/VHDL
Interleaver and Deinterleaver VHDL Source Code
VHDL source code for an interleaver/deinterleaver, based on corresponding MATLAB code. Includes links to other useful VHDL code examples.

VHDL Code for Basic Logic Gates

Explore VHDL Digital Logic Gates, Mux & Encoders

Continue Learning VHDL

Related Posts