Parallel Load Shift Left Register Verilog Code

This document provides the Verilog code and test bench code for a Parallel Load Shift Left Register.

Parallel Load Shift Left Register Verilog Code

The following is the Verilog code for the Parallel Load Shift Left Register.

module plsl(pl, sl, slin, Din, clk, reset, Q);
  input pl, sl, slin, clk, reset;
  input [7:0] Din;
  output [7:0] Q;
  reg [7:0] Q;

  always @ (posedge clk) begin
    if (~reset) begin
      if (sl) begin
        Q <= {Q[6:0],slin}; // Shift Left Operation
      end else if (pl) begin
        Q <= Din;           // Parallel Load Operation
      end
    end
  end

  always @ (posedge reset) begin
    Q <= 8'b00000000; // Reset the register
  end

endmodule

Explanation:

• module plsl(...): Defines the module named plsl with its input and output ports.
• input pl, sl, slin, clk, reset;: Declares the input signals:
  • pl: Parallel Load enable.
  • sl: Shift Left enable.
  • slin: Serial input for shift left.
  • clk: Clock signal.
  • reset: Reset signal (active low in the load/shift section, active high in the reset section).
• input [7:0] Din;: Declares an 8-bit input for parallel data load.
• output [7:0] Q;: Declares an 8-bit output register to store the register’s value.
• reg [7:0] Q;: Declares Q as a register since its value is updated within the always block.
• always @ (posedge clk): This block executes on the rising edge of the clock.
• if (~reset): Checks if the reset is inactive (low in the load/shift section).
• if (sl): If the shift left enable (sl) is active, it performs a shift left operation, shifting in slin. Q <= {Q[6:0], slin}; concatenates the 7 least significant bits of Q with slin to perform the shift.
• else if (pl): If the parallel load enable (pl) is active, it loads the value of Din into the register Q.
• always @ (posedge reset): This block executes on the rising edge of the reset. When reset is high, the register Q is initialized to all zeros.

Test Code for Parallel Load Shift Left Register

The following is the test bench code for the Parallel Load Shift Left Register.

module main;
  reg clk, reset, slin, sl, pl;
  reg [7:0] Din;
  wire [7:0] q;

  plsl plsl1(pl, sl, slin, Din, clk, reset, q);

  initial begin
    forever begin
      clk <= 0;
      #5 clk <= 1;
      #5 clk <= 0;
    end
  end

  initial begin
    reset = 1;
    #12 reset = 0;
    #90 reset = 1;
    #12 reset = 0;
  end

  initial begin
    sl = 1;
    pl = 0;
    Din = 8'h42;
    #50 sl = 0;
    #12 pl = 1;
    #5 Din = 8'h21;
    #20 pl = 0;
    sl = 1;
  end

  initial begin
    forever begin
      slin = 0;
      #7 slin = 1;
      #8 slin = 0;
    end
  end

endmodule

Explanation:

• module main;: Defines the test bench module.
• reg clk, reset, slin, sl, pl;: Declares the input signals as registers, as they are driven within the test bench.
• reg [7:0] Din;: Declares the 8-bit data input as a register.
• wire [7:0] q;: Declares the output of the PLSL module as a wire. Note that the original code used Q for both the output of the module and the register inside the module. This has been corrected to avoid confusion: the output of the plsl1 instance is connected to the wire q, while the register inside the module is still named Q.
• plsl plsl1(pl, sl, slin, Din, clk, reset, q);: Instantiates the plsl module (named plsl1) and connects the signals.
• initial begin ... end: These blocks are executed only once at the beginning of the simulation.
• The first initial block generates a clock signal with a period of 10 time units.
• The second initial block generates a reset signal. It’s initially high, then goes low, then high again, and finally low again to test the reset functionality.
• The third initial block sets up the sl, pl, and Din signals to test the shift left and parallel load operations.
• The fourth initial block generates the serial input slin.