Verilog Code for Binary Up/Down Counter

This article provides Verilog HDL code for a binary up/down counter.

Symbol and Truth Table

The following is the truth table of the binary up/down counter:

Verilog Code

module bin_as(clk,clr,dir, temp);
  input clk,clr,dir;
  output reg[3:0] temp;

  always@(posedge clk,posedge clr)
  begin
    if(clr==0)
    begin
      if(dir==0)
        temp=temp+1;
      else
        temp=temp-1;
    end
    else
      temp=4'd0;
  end
endmodule

Simulation Result

Here’s the simulation result of the above Verilog code: