4 Bit BCD Synchronous Reset Counter Verilog Code
This page of Verilog source code section covers 4 Bit BCD Synchronous Reset Counter Verilog Code. The block diagram and truth table of 4 Bit BCD Synchronous Reset Counter Verilog Code is also mentioned.
Block Diagram of 4 Bit BCD Synchronous Reset Counter
Truth Table of 4 Bit BCD Synchronous Reset Counter
4 Bit BCD Synchronous Reset Counter Verilog Code
module bin_sync( clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bin_out=bin_out+4'd1;
else
bin_out=4'd0;
end
endmodule
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bin_out=bin_out+4'd1;
else
bin_out=4'd0;
end
endmodule
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