JESD204B vs LVDS | difference between JESD204B and LVDS
This page compares JESD204B vs LVDS and mentions difference between JESD204B and LVDS in tabular format.
Features | JESD204B | LVDS |
---|---|---|
Full form | Name has been derived from JEDEC (Joint Electron Device Engineering Council) | Low Voltage Differential Signaling |
Release year | 2011 | 2001 |
Max. lane rate in Gbps | 12.5 | 1.0 |
Number of Data clock lines | Embedded | 2 (i.e. 1 pair) |
Number of data lines 16 bit, 250 MSs/sec ADC |
2 to 4 (i.e. 1 to 2 pair). This depends on mode. | 32 (i.e. 16 pairs) |
Matching needed | Not required | Required |
Phase aligned sampling for multiple ADCs | Yes | possible but difficult to incorporate |
Interface coding efficiency | 84% for 8B/10B type | 100% (no coding case) |
Multiple lanes | Supported | Not supported |
Lane synchronization | supported | not supported |
multi-device synchronization | Supported | not supported |
deterministic latency | Yes | No |
Harmonic clocking | Yes | No |
REFERENCEs | Refer LVDS vs TTL>> |
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