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JESD204B vs JESD204C | difference between JESD204B and JESD204C

This page compares JESD204B vs JESD204C and mentions difference between JESD204B and JESD204C.

Introduction: These are high speed interface specifications published by JEDEC (Joint Electron Devices Engineering Council). The three published specifications include JESD204A, JESD204B and JESD204C. These interfaces are designed to connect fast ADCs/DACs to high speed FPGAs, Processors and ASICs.



Following are the features of JESD204B.
• It is published in 2008 which is enhancement to previous version i.e. JESD204A. Device subclass 0 is backward compatible to JESD204A. The other subclasses include 1 and 2.
• It supports speed up to 12.5 Gb/sec compare to 3.125 Gb/sec supported by JESD204A.
• Supports single or multiple lanes, serial lane alignment and monitoring, lane synchronization
• Modular design which supports multi-device synchronization
• Supports deterministic latency
• 8B/10B encoding, scrambling and descrambling etc.
• Refer standard specifications published on jedec.org for complete information on JESD204B.


Following are the features of JESD204C.
• Backward compatible with JESD204A and JESD204B standard versions.
• It supports interface requirements of high megabit and gigabit data rates for various applications such as 5G cellular equipments, test equipments, medical devices, military warfare and so on.
• It supports all the features of JESD204B and added new benefits.
• It supports device subclasses viz. subclass-0 and subclass-1. Subclass-0 supports no deterministic latency. Subclass-1 uses SYSREF signal to support deterministic latency.
• LEMC counter based on E range from 1 to 256
• 64/66 encoding, scrambling and descrambling
• No FEC support
• Refer standard specifications published on jedec.org for complete information on JESD204C.

Tabular difference between JESD204B and JESD204C

Following table mentions difference between JESD204B and JESD204C.

Features JESD204B JESD204C
Release year 2011 2017
Data Rate (Maximum) 12.5 Gb/sec 32.5 Gb/sec
Encoding schemes 8B/10B 8B/10B, 64B/66B, 64B/80B
DC Balance Good Better than JESD204B
Clock recovery Good Better than JESD204B
Data alignment Good Better than JESD204B
Bit Overhead 25% 3.125%, Much smaller than JESD204B
Scrambling polynomial 1 + X14 + X15 1 + X39 + X58
CRC encoding / Decoding Not supported Supported, CRC-12 is used to compute parity bits
Deterministic latency Supported, in terms of RBD frame cycles Supported, in terms of number of RBD characters
Transceiver classes Not supported Supported
SYNC • Timing of SYNC~ signal are relative to frame clock
• Supports hard wired SYNC interface
• Timing of SYNC~ signal are relative to sync generation and sync detection clocks
• Supports hard wired and soft SYNC interface
Phase synchronization • Same as JESD204A, except synchronous to local multi-frame clock (LMFC) instead of frame clock
• SYSREF (subclass-1); SYNC (subclass-2)
• LMFC (local multi-frame clock), Local Extended multi-block clock
• SYSREF (subclass-1 : 8B/10B, 64B/66B, 64B/80B); SYNC (subclass-2 : 8B/10B)
Maximum K frames in multi-frame 32 256
Programmable ILAS length Supported Not supported (Fixed to 4)

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