Any Sequence Counter VHDL Code | Any Sequence Counter HDL Code

This page of VHDL source code mentions Any Sequence Counter VHDL Code.

Any Sequence Counter VHDL Code

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seq is
port ( clk : in std_logic;
z : out std_logic_vector (2 downto 0));
end seq;
architecture behavioral of seq is
signal clkdiv: std_logic;
signal div:std_logic_vector(22 downto 0);
begin
process(clk) is
begin
if(rising_edge(clk)) then
div<= div + '1';
end if;
end process;
clkdiv<=div(22);
process(clkdiv)
variable q,qp: std_logic_vector(1 downto 0);
begin
if (rising_edge(clkdiv)) then
qp(1):= q(1) xor q(0);
qp(0):= not q(0);
z(2)<= q(1) or q(0);
z(1)<= q(1) and (not q(0));
z(0)<= not q(1) and q(0);
end if;
q<=qp ;
end process;
end;


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