8 to 3 encoder without priority VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity encoder8_3 is
port (en: in std_logic;
a_in: in std_logic_vector (7 downto 0);
y_op: out std_logic_vector (2 downto 0));
end encoder8_3;
architecture behavioral of encoder8_3 is
begin
process (en, a_in)
begin
if (en = '1') then
y_op <= "ZZZ";
else
case (a_in) is
when "00000001" =< y_op <= "000";
when "00000010" =< y_op <= "001";
when "00000100" =< y_op <= "010";
when "00001000" =< y_op <= "011";
when "00010000" =< y_op <= "100";
when "00100000" =< y_op <= "101";
when "01000000" =< y_op <= "110";
when "10000000" =< y_op <= "111";
when others =< null;
end case;
end if;
end process;
end;