Half Adder HDL Verilog Code

This page of verilog sourcecode covers HDL code for half adder, half substractor, full substractor using verilog.

The half adder truth table and schematic (fig-1) is mentioned below. The boolean expressions are:

S= A (EXOR) B
C=A.B

Half Adder Schematic

Half Adder Verilog code

module ha ( a, b, s, c) 

input a, b;

output s, c;

assign s= a ^ b;

assign c= a & b; 

end module

Half Substractor

The half substractor truth table and schematic (fig-2) is mentioned below. The boolean expressions are:

D= A (EXOR) B
Br=A'.B

Half substractor Schematic

Half Substractor Verilog code

module hs ( a, b, d, br) 

input a, b; 

output d, br;

assign d= a ^ b;

assign br= ~a & b;

end module

Full Substractor

The full substractor truth table and schematic (fig-3) is mentioned below. The boolean expressions are:

D= A (EXOR) B (EXOR) C
Br=A'.B + B.Cin + A'.Cin

Full substractor Schematic

Full Substractor Verilog code

module fs ( a, b, c, d, br) 

input a, b, c;

output d, br;

assign d= a ^ b ^ c;

assign br=(( ~a)& (b ^ c)) | (b & c);

end module

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