8 to 3 encoder HDL Verilog Code
This page of verilog sourcecode covers HDL code for 8 to 3 encoder with priority using verilog.
Truth Table and Schematic
Following is the truth table and schematic of the 8 to 3 parity encoder.
| En | I7 | I6 | I5 | I4 | I3 | I2 | I1 | I0 | Z2 | Z1 | Z0 | enx | V |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | X | X | X | X | X | X | X | X | 1 | 1 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | X | 1 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 0 | X | X | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 0 | X | X | X | 1 | 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 | X | X | X | X | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | X | X | X | X | X | 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | X | X | X | X | X | X | 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | X | X | X | X | X | X | X | 0 | 0 | 0 | 0 | 1 |
Verilog code
module enc8_3 (I, en, y, v);
input [7:0]I;
input en;
output v;
output [2:0]y;
sig y; sig v;
always @ (en, I)
begin
if(en= =0)
v=0;
else
v=1;
end
if ( I[7]= =1 & en= =1) y=3�b111;
else if ( I[6]==1 & en==1) y=3�b110;
else if ( I[5]==1 & en==1) y=3�b101;
else if ( I[4]==1 & en==1) y=3�b100;
else if ( I[3]==1 & en==1) y=3�b011;
else if ( I[2]==1 & en==1) y=3�b010;
else if ( I[1]==1 & en==1) y=3�b001;
else if ( I[0]==1 & en==1) y=3�b000;
else y=3�b000;
end
end module
Simulation result
RF and Wireless tutorials
WLAN 802.11ac 802.11ad wimax Zigbee z-wave GSM LTE UMTS Bluetooth UWB IoT satellite Antenna RADAR