8-to-3 Priority Encoder: Verilog Code

This page provides Verilog source code for an 8-to-3 encoder with priority. It includes the truth table, schematic, and the Verilog code itself.

Truth Table and Schematic

Here’s the truth table and schematic of the 8-to-3 encoder:

Note: In the truth table, ‘X’ represents a “don’t care” condition. The encoder prioritizes higher-order inputs.

Verilog Code

module enc8_3 (I, en, y, v);
  input [7:0] I;
  input en;
  output v;
  output [2:0] y;

  reg v;
  reg [2:0] y;

  always @ (en, I) begin
    if (en == 0)
      v = 0;
    else
      v = 1;

    if (I[7] == 1 && en == 1)
      y = 3'b111;
    else if (I[6] == 1 && en == 1)
      y = 3'b110;
    else if (I[5] == 1 && en == 1)
      y = 3'b101;
    else if (I[4] == 1 && en == 1)
      y = 3'b100;
    else if (I[3] == 1 && en == 1)
      y = 3'b011;
    else if (I[2] == 1 && en == 1)
      y = 3'b010;
    else if (I[1] == 1 && en == 1)
      y = 3'b001;
    else if (I[0] == 1 && en == 1)
      y = 3'b000;
    else
      y = 3'b000;
  end
endmodule

Explanation:

• module enc8_3 (I, en, y, v);: Defines the module named enc8_3 with inputs I (8-bit input), en (enable), and outputs y (3-bit output), and v (valid output).
• input [7:0] I;: Declares I as an 8-bit input vector.
• input en;: Declares en as a single-bit input (enable).
• output v;: Declares v as a single-bit output (valid). It indicates if any of the inputs are high, and the encoder is enabled.
• output [2:0] y;: Declares y as a 3-bit output vector, representing the encoded value.
• reg v;: Declares v as a register.
• reg [2:0] y;: Declares y as a register.
• always @ (en, I) begin ... end: This block executes whenever there is a change in either the en input or any bit of the I input.
• if (en == 0) v = 0; else v = 1;: If the enable input en is 0, then the valid output v is set to 0. Otherwise, v is set to 1.
• The series of if-else if statements checks each input bit from I[7] down to I[0]. If a particular input bit is high (1) and the enable is high, the corresponding 3-bit code is assigned to the output y. This implements the priority encoding, where higher-order inputs take precedence.
• else y = 3'b000;: If none of the inputs I[7:0] are high and the enable is high, the output y defaults to 3'b000.

Simulation Result

Here is an example simulation result:

This simulation result demonstrates the functionality of the 8-to-3 encoder. You can see how the output y changes based on the input I, and the v (valid) signal goes high when the encoder is enabled and there is a valid input.