8 to 1 Multiplexer HDL Verilog Code
This page of verilog sourcecode covers HDL code for 8 to 1 Multiplexer using verilog.
Symbol
Following is the symbol and truth table of 8 to 1 Multiplexer.
Truth Table
| Sel2 | Sel1 | Sel0 | Z |
|---|---|---|---|
| 0 | 0 | 0 | A |
| 0 | 0 | 1 | B |
| 0 | 1 | 0 | C |
| 0 | 1 | 1 | D |
| 1 | 0 | 0 | E |
| 1 | 0 | 1 | F |
| 1 | 1 | 0 | G |
| 1 | 1 | 1 | H |
Verilog code
module mux8_1
input [7:0]I;
output [2:0]S;
output y;
input en;
reg y;
always @(en,S,I,y);
begin
if (en= =1)
begin
if (s= =000 y=I[0];
else if (s==001) y=I[1];
else if (s==001) y=I[2];
else if (s==001) y=I[3];
else if (s==001) y=I[4];
else if (s==001) y=I[5];
else if (s==001) y=I[6];
else if (s==001) y=I[7];
end
else y=0;
end
end
end module
Simulation result
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