RF Frequency Synthesizer Design: Block Diagram & Components

The device used to select an RF carrier frequency from a pool of frequencies in a wireless system is called an RF synthesizer. It is used as a variable RF frequency generator source. The tuning of the RF frequency depends on the step size. It is responsible for generating stable and tunable RF signals at various frequencies.

Let’s learn about RF frequency synthesizer design, its block diagram, components, and how it generates stable and precise RF signals for communication systems. It is used for various applications such as in RF transceivers, base stations, mobile subscribers, test and measurement equipment such as VSG (vector signal generator), VSA (vector signal analyzer), and so on. Its usage spans across multiple technologies, especially satellite communication, terrestrial microwave communication, wireless communication, radar, etc.

Frequency Synthesizer Block Diagram

An RF frequency synthesizer typically consists of several components with a Phase Locked Loop (PLL) and Voltage Controlled Oscillator (VCO) being key elements.

As shown in the frequency synthesizer block diagram, the PLL consists of a reference frequency, phase detector, loop filter, frequency divider, and VCO. The PLL is a closed-loop feedback system that compares the output frequency of the VCO with a reference frequency. It adjusts the control voltage applied to the VCO to minimize the phase difference between the two signals, thereby locking the output frequency to the reference frequency.

Frequency synthesizer output frequency is mathematically calculated using the following equations as per its type.

1. $F_{out} = N * (F_r / R)$ , for Integer PLL
2. $F_{out} = (N + F) * (F_r / R)$, for fractional PLL

As mentioned here, the output frequency of the synthesizer is a multiple of the input frequency, hence often the frequency synthesizer is called a frequency multiplier.

The output of the frequency synthesizer can be obtained by either fixing $F_r$ and varying $N$ or varying $F_r$ and fixing $N$. The RF synthesizer design example mentioned below is for the second case.

Channel spacing = $F_{vco} / N$ or $F_r / R$.

Frequency Synthesizer Components Functions/Working

Let us understand functions of various components of frequency synthesizer.

• VCO: The VCO is responsible for producing an oscillating RF signal whose frequency can be varied by applying a control voltage. The VCO’s output frequency is directly related to the input control voltage.

• Phase Detector (PD): As shown in the RF synthesizer block diagram, the phase detector/comparator compares two input signals and produces a DC voltage (error voltage) based on the phase difference of the two. A phase detector can be considered as a simple EX-OR gate.

• Loop filter: It is a simple Low Pass Filter, which removes high-frequency noise and produces a DC level.

• Frequency Dividers: The VCO output frequency is compared with the reference frequency and adjusted until it is equal to the input frequency. Divide by R and Divide by N are simple frequency dividers. Frequency dividers are used in synthesizer design to divide down the VCO output frequency to generate the desired output frequency with better resolution.

• Control Interface: Provides a means for external control and programming of the synthesizer parameters, such as frequency and modulation settings.

• Output Buffer/Amplifier: Amplifies and conditions the output signal for transmission or further processing.

PLL operates in three stages as mentioned below.

1. Free running: Before the input is applied to the PLL, PLL is said to be in free-running state.
2. Capture: As soon as the input frequency is applied, the VCO frequency will start to change, and PLL is said to be in capture mode.
3. Phase Lock: VCO frequency continues to change till it is equal to the input reference frequency, and PLL in this condition is said to be in phase locked state.

Example of RF Synthesizer Design

Let us understand the design of a frequency synthesizer using a PLL IC, DDS chip, VCO, and other components with the following desired specifications:

• Output frequency: 950-1450 MHz
• Step size: 1 MHz
• Low Phase noise: -88 dBc at 1 KHz offset
• Spurious: -70dBc
• Harmonics: less than -20dBc typically
• External Reference: 10 MHz

Consider following rules of thumb during RF synthesizer design.

• Switching time approximately equals to 50/$F_{comp}$, where $F_{comp}$ is the comparison frequency at the input of the Phase comparator/detector.
• Switching time approx. equal to 2.5/$F_{lbw}$, where $F_{lbw}$ is the loop bandwidth of the loop filter.
• Loop filter loop bandwidth= 1/10 ($F_{comp}$).

Following steps are followed during design.

• As mentioned here, the design of the frequency synthesizer is done by buying out PLL chip, VCO chip, and DDS chip. We have selected, PLL chip as ADF-4252 from Analog devices, VCO as V585ME40 from ZCOMM, and DDS chip as AD9851 from Analog devices.

• The loop filter needs to be designed based on the rules of thumb mentioned above. Loop filter design can be done by entering required parameters.

• In the design of the rf synthesizer, various parameters are optimized based on requirement. For example, for the case where switching time is not so critical, then the choice of loop parameters will be determined by phase noise and spurious specifications.

Loop filter tools are available on the various websites such as https://www.ti.com/, https://www.analog.com/ and www.circuitsage.com .

Conclusion

The RF frequency synthesizer design involves the integration of a Phase-Locked Loop (PLL) and a Voltage-Controlled Oscillator (VCO) to generate stable and tunable radio frequency signals. The synthesizer includes a control interface for user adjustments. RF frequency synthesizers are the cornerstone of modern communication systems, ensuring accuracy and stability. Designing them requires understanding their components and architecture.