GSM Control Channel Processing Through Physical Layer

Introduction

This article delves into the processing of GSM control channels (signalling channels) through the physical layer, specifically covering SACCH, FACCH/F, FACCH/H, BCCH, PCH, AGCH, CBCH, NCH, SDCCH, RACH, and SCH channels. The information presented aligns with the 3GPP TS 45.003 standard.

SACCH Control Channel Processing

As depicted in the figure, the following steps outline the SACCH information flow through the physical layer:

• Step 1: SACCH information, totaling 184 bits, is augmented with 40 bits using a shortened binary cyclic code (Fire code), resulting in 224 bits.
• Step 2: 4 tail bits are added, bringing the total to 228 bits.
• Step 3: These 228 bits are then processed by a Convolutional Encoder (C.E.) with a rate of 1/2, which expands the data to 456 bits. The Go and G1 polynomials are defined in the 3GPP specifications.
• Step 4: This 456-bit stream undergoes block interleaving and is mapped onto 4 GSM bursts.
• Step 5: The data proceeds to GMSK modulation and is then sent to the RF section for upconversion and amplification before transmission. The channel is mapped to its designated position within a larger GSM 51-frame multiframe structure.
• Step 6: Two bits, hl(B) and hu(B), serve as flags to indicate control channel signaling. For a SACCH control channel, both are set to 1.

Note: Fire code generator polynomial, g(D) = (D²³ + 1) (D¹⁷ + D³ + 1)

FACCH Full Rate Control Channel Processing

• Step 1: 184 bits undergo block code processing similar to the SACCH channel.
• Step 2: Block-coded data is then convolutionally encoded in a manner analogous to SACCH.
• Step 3: Interleaving is performed as with the TCH/FS channel.
• Step 4: The 456 interleaved data bits are mapped to 8 consecutive bursts (identical to TCH/FS).

Note: hu(B) equals 1 for the first 4 bursts when even-numbered bits are stolen. hl(B) = 1 for the last 4 bursts when odd-numbered bits are stolen.

FACCH Half Rate Control Channel Processing

• Step 1: 184 bits pass through a block coder and convolutional encoder, identical to the SACCH channel processing.
• Step 2: The encoded data is interleaved, mirroring the process used for TCH/FS.
• Step 3: The interleaved data is mapped onto 6 consecutive bursts.

Note: hu(B) equals 1 for the first 2 bursts when even-numbered bits are stolen. hu(B) equals 1 and hl(B) = 1 for the middle 2 bursts when all bits are stolen. hl(B) equals 1 for the last 2 bursts when odd-numbered bits are stolen.

BCCH/PCH/AGCH/CBCH/NCH/SDCCH Control Channel Processing

For BCCH, PCH, AGCH, CBCH, NCH, and SDCCH, the processing is performed in a similar fashion to the SACCH control channel.

RACH Control Channel Processing

RACH can carry either 8 or 11 information bits. The encoding process for 8 bits is described below:

• Step 1: 6 bits of BSIC data are added, along with 6 parity bits, resulting in 12 bits. These are combined with 2 initial bits of information.
• Step 2: 4 tail bits are added to the 14 bits of this data, producing 18 bits.
• Step 3: The 18 bits are passed through a Convolutional encoder with a rate of 1/2 (same as TCH/FS), generating 36 encoded data bits.

SCH Control Channel Processing

• Step 1: 25 information bits of SCH data are added with 10 parity bits, totaling 35 bits.
• Step 2: 4 tail bits are added to these 35 bits, resulting in 39 bits.
• Step 3: The 39 bits are passed through a Convolutional encoder, yielding 78 bits (same as TCH/FS processing).

GSM Standard References

• 3GPP TS 45.002 describes burst building and burst multiplexing
• 3GPP TS 45.003 describes coding and interleaving
• 3GPP TS 45.004 describes differential encoding and modulation
• 3GPP TS 45.005 describes transmitter, receiver and antenna part
• 3GPP TS 43.020 & 23.221 describes encryption/ciphering part