Posts tagged: Digital Logic

Showing 20 posts (Page 2 of 3)

Any Sequence Counter VHDL Code

VHDL source code for an 'Any Sequence Counter', including code snippet and useful links to VHDL and Verilog resources.

Asynchronous vs. Synchronous Counters: Key Differences

Explore the fundamental differences between asynchronous and synchronous counters, focusing on clocking, speed, count sequence, and decoding errors.

digital counter asynchronous counter synchronous counter

BCD Code vs. Excess-3 Code: Key Differences Explained

Explore the distinctions between Binary Coded Decimal (BCD) and Excess-3 code. Understand their conversion, representation, and applications.

binary code bcd excess-3

Binary to Gray Code Conversion Explained

Explore the conversion between binary and Gray code, including logic diagrams, boolean functions, and VHDL/Verilog code examples.

digital logic binary code gray code

Binary to Gray Code Conversion in VHDL

VHDL code for converting binary numbers to Gray code using XOR operations. Efficient implementation for digital design.

vhdl binary gray code

Carry Select Adder and Carry Skip Adder: VHDL Code and Explanation

Explore Carry Select and Carry Skip adders with VHDL code. Learn their implementations and advantages in digital circuit design.

adder carry select carry skip

D Flip-Flop VHDL Source Code

VHDL source code for a D Flip-Flop implementation, including reset and clock-triggered data capture.

vhdl flip-flop d flip-flop

D Latch VHDL Source Code

VHDL source code implementation of a D Latch, a fundamental digital logic circuit.

vhdl d latch source code

DeMorgan's Theorem: Simplifying Logical Expressions

Learn the basics of DeMorgan's Theorem with rules and examples for simplifying logical expressions in Boolean algebra. Includes a handy mnemonic.

boolean algebra logic expression demorgan theorem

Emitter Coupled Logic (ECL) Circuits Explained

Explore Emitter Coupled Logic (ECL) circuits: their key characteristics, implementation using bipolar junction transistors (BJTs), and examples of ECL inverter, NAND, and NOR gates.

logic circuit emitter coupled logic ecl

Fanout vs. Noise Margin: Key Differences Explained

Understand the differences between fanout and noise margin in logic gates. Learn their definitions, importance, and calculations for optimal circuit performance.

fanout noise margin logic gate

Flip-Flop Design Using LabVIEW VIs: SR, JK, T, and D

Explore the design of SR, JK, T, and D flip-flops using LabVIEW Virtual Instruments (VIs) with block diagrams and truth tables.

labview flip flop vi

Full Adder Verilog HDL Code

Verilog HDL implementation of a full adder, including truth table, code, and simulation results.

verilog hdl full adder

Full Adder VHDL Source Code

VHDL source code implementation of a full adder, including equations for Sum and Carry Out.

vhdl adder source code

JK Flip-Flop VHDL Source Code

VHDL source code implementation of a JK Flip-Flop with reset functionality. Includes behavioral architecture and links to other VHDL code examples.

vhdl flip-flop jk flip-flop

N-Stage Johnson Counter: VHDL Code and Applications

Explore the n-stage Johnson counter with VHDL code, combinational logic, applications, and examples.

johnson counter vhdl code digital logic

Shift Left Shift Right Register Verilog Code and Test Bench

Verilog code and test bench for a Shift Left Shift Right Register. Includes module declaration, reset, shift conditions, and explanation.

verilog shift register test bench

SISO vs. SIPO vs. PISO vs. PIPO: Shift Register Types

Explore the differences between SISO, SIPO, PISO, and PIPO shift registers, their configurations, and clock pulse requirements for data input and output.

shift register serial communication parallel communication

T Flip-Flop VHDL Source Code

VHDL source code for a T Flip-Flop implementation, including entity and architecture definitions.

vhdl flipflop t flipflop

T, D, SR, JK Flip-Flop Verilog HDL Code Examples

Explore Verilog HDL code implementations for T, D, SR, and JK flip-flops, complete with truth tables and simulation results.

verilog hdl flip flop