Full Adder VHDL source code

This page of VHDL source code covers Full Adder vhdl code.

VHDL Code

library IEEE;			

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entuty FA is

Port(a,b,ci : in STD_LOGIC; s,co : out STD_LOGIC);

end FA;

architecture Behavioral of FA is

begin



s<= a xor b xor ci;

co<=(a and b) or (b and ci) or ( ci and a);

end Behavioral;

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