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All Logic Gates VHDL Code

This page of VHDL source code section covers All Logic Gates VHDL Code.

All Logic Gates VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity gates is
port (a_in,b_in: in std_logic;
out std_logic);
end gates;
architecture dataflow of gates is
not_op<= not a_in;
and_op<= a_in and b_in;
nand_op<= a_in nand b_in;
or_op<= a_in or b_in;
nor_op<= a_in nor b_in;
xor_op<= a_in xor b_in;
xnor_op<= a_in xnor b_in;
end ;


Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial

USEFUL LINKS to Verilog Codes

Following are the links to useful Verilog codes.
Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates

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