4 Bit Binary Asynchronous Reset Counter VHDL Code
This page of VHDL source code section covers 4 Bit Binary Asynchronous Reset Counter VHDL Code. The block diagram and truth table of 4 Bit Binary Asynchronous Reset Counter VHDL Code is also mentioned.
Block Diagram of 4 Bit Binary Asynchronous Reset Counter
Truth Table of 4 Bit Binary Asynchronous Reset Counter
4 Bit Binary Asynchronous Reset Counter VHDL Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bin_asyn is
port (clk, rst: in std_logic;
bin_out: out std_logic_vector(3 downto o));
end bin_syn;
architecture behavioral of bin_syn is
signal div:std_logic_vector(22 downto 0);
signal clkdiv:std_logic;
signal temp:std_logic_vector(3 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
div<=div+'1';
end if;
end process;
clkdiv<=div(22);
process (clkdiv,rst)
begin
if (rst='0') then
temp<="0000";
elsif (rising_edge(clkdiv))then
temp<=temp+'1';
end if;
end process;
bin_out<=temp;
end ;
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