T, D, SR, JK flipflop HDL Verilog Code
This page of verilog sourcecode covers HDL code for T flipflop, D flipflop, SR flipflop and JK flipflop using verilog.
T flipflop Symbol
Following is the symbol and truth table of T flipflop.
T Flipflop truth table
| Rst | T | Clk | q |
|---|---|---|---|
| 1 | 0 | 1 | q |
| 1 | 1 | 1 | qb |
| 1 | X | No positive edge | Previous state |
| 0 | X | X | 0 |
T Flipflop Verilog code
module tff(t,clk,rst, q,qb);
input t,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0) begin
if(t==1) begin
temp=~ temp;
end
else
temp=temp;
end
q=temp;qb=~temp;
end
end module
Simulation result
D flipflop Symbol
Following is the symbol and truth table of D flipflop.
D Flipflop truth table
| clk | d | q | qb |
|---|---|---|---|
| X | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
D Flipflop Verilog code
module dff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0)
temp=d;
else
temp=temp;
q=temp;
qb=~ temp ;
end
end module
Simulation result
SR flipflop Symbol
Following is the symbol and truth table of SR flipflop.
SR Flipflop truth table
| rst | pr | Clk | s | r | q | qb |
|---|---|---|---|---|---|---|
| 1 | X | X | X | X | 0 | 1 |
| 0 | 1 | X | X | X | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | Qb | Qbprevious |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 |
SR Flipflop Verilog code
module srff(s,r,clk,rst, q,qb);
input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end
qb=~q;
end
end module
Simulation result
JK flipflop Symbol
Following is the symbol and truth table of JK flipflop.
JK Flipflop truth table
| Rst | Clk | J | K | Q | Qb |
|---|---|---|---|---|---|
| 1 | 1 | 0 | 0 | Previous | state |
| 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | Qb | Q |
| 1 | No +ve edge | - | - | Previous | state |
| 0 | - | - | - | 0 | 1 |
JK Flipflop Verilog code
module jkff(j,k,clk,rst, q,qb);
input j,k,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]jk;
always@(posedge clk,posedge rst)
begin
jk={j,k};
if(rst==0)
begin
case (jk)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=~q;
default: begin end
endcase
end
else
q=1'b0;
qb=~q;
end
end module
Simulation result
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