Shift Left Shift Right Register verilog code and test bench
This page covers Shift Left Shift Right Register verilog code and mentions test bench code for Shift Left Shift Right Register.
Shift Left Shift Right Register Verilog code
Following is the verilog code of Shift Left Shift Right Register.
module slsr(sl, sr, din, clk, reset,Q);
input sl, sr, din, clk, reset;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= #2 {Q[6:0],din};
end
else if (sr) begin
Q <= #2 {din, Q[7:1]};
end
end
end
always @ (posedge reset) begin
Q<= 8'b00000000;
end
endmodule
input sl, sr, din, clk, reset;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= #2 {Q[6:0],din};
end
else if (sr) begin
Q <= #2 {din, Q[7:1]};
end
end
end
always @ (posedge reset) begin
Q<= 8'b00000000;
end
endmodule
Shift Left Shift Right Register Test bench code
Following is the test script code for Shift Left Shift Right Register.
module main;
reg clk, reset, din, sl, sr;
wire [7:0] q;
slsr slsr1(sl, sr, din, clk, reset, q);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
initial begin
sl = 1;
sr = 0;
#50
sl = 0;
#12
sr = 1;
end
initial begin
forever begin
din = 0;
#7
din = 1;
#8
din = 0;
end
end
endmodule
reg clk, reset, din, sl, sr;
wire [7:0] q;
slsr slsr1(sl, sr, din, clk, reset, q);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
initial begin
sl = 1;
sr = 0;
#50
sl = 0;
#12
sr = 1;
end
initial begin
forever begin
din = 0;
#7
din = 1;
#8
din = 0;
end
end
endmodule
Verilog source codes
Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates
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