D flip flop with synchronous Reset | VERILOG code with test bench
This D Flipflop with synchronous reset covers symbol, verilog code, test bench, simulation and RTL Schematic. The test bench for D flip flop in verilog code is mentioned.
D Flip flop Symbol
D Flip flop Verilog code
module d_flipflop_synrst(data_in,data_out,clock,reset);
input data_in;
input clock,reset;
output reg data_out;
always@(posedge clock)
begin
if(reset)
data_out<=1'd0;
else
data_out<=data_in;v end
endmodule
input data_in;
input clock,reset;
output reg data_out;
always@(posedge clock)
begin
if(reset)
data_out<=1'd0;
else
data_out<=data_in;v end
endmodule
d flip flop verilog code testbench
module Tb_dflipflop_synrst();
reg data_in;
reg clock,reset;
wire data_out;
d_flipflop_synrst UUT(.data_in(data_in),
.data_out(data_out),
.clock(clock),
.reset(reset));
initial begin
// Initiliase Input Stimulus
data_in = 0;
clock = 0;
reset=0;
end
always #100 clock=~clock;
//Stimulus
initial
begin
#200 data_in = 1'b1;
reset = 1'b1;
#200 data_in = 1'b1;
reset = 1'b1;
#300 data_in = 1'b1;
reset=1'b0;
#600 data_in = 1'b0;
#500 data_in = 1'b1;
#200 data_in = 1'b0;
#400 $stop;
end
endmodule
reg data_in;
reg clock,reset;
wire data_out;
d_flipflop_synrst UUT(.data_in(data_in),
.data_out(data_out),
.clock(clock),
.reset(reset));
initial begin
// Initiliase Input Stimulus
data_in = 0;
clock = 0;
reset=0;
end
always #100 clock=~clock;
//Stimulus
initial
begin
#200 data_in = 1'b1;
reset = 1'b1;
#200 data_in = 1'b1;
reset = 1'b1;
#300 data_in = 1'b1;
reset=1'b0;
#600 data_in = 1'b0;
#500 data_in = 1'b1;
#200 data_in = 1'b0;
#400 $stop;
end
endmodule
D flip flop with synchronous reset Simulation
D flip flop RTL Schematic
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