SISO vs SIPO vs PISO vs PIPO-difference between SISO,SIPO,PISO,PIPO shift registers
This page on SISO vs SIPO vs PISO vs PIPO describes basic difference between SISO, SIPO, PISO, PIPO shift register types.
In shift register each CLK PULSE will shift content of register by one bit to the 'right' or 'left'. The serial input will determine what content goes into the 'left most flipflop' during the shift. We will compare SISO, SIPO, PISO and PIPO shift registers of 4 bit in size. In 'n-bit' register, it needs 'n' clock pulses to enter 'n bit' of data serially.
The shift register concept is widely used in DSP based algorithms as each shift left corresponds to multiplying the data by 2 and each shift right corresponds to dividing the data by 2.
SISO-Serial IN Serial OUT shift register
Figure-1 depicts SISO shift register type.
There are four types of SISO as mentioned below:
• Shift left without rotate
• Shift right without rotate
• Shift left with rotate
• Shift right with rotate
• In right shift SISO register, LSB data is applied at the MSB Flipflop such as D flipflop.
• SISO register is used to provide n clock pulse delay to the input data.
• If 'T' is the time period of one clock pulse, then total delay provided by SISO is 'n*T'. • In left shift SISO register, MSB data is applied to LSB Flipflop i.e. D Flipflop.
PIPO-Parallel IN Parallel Out storage register
Figure-2 depicts PIPO register type. PIPO type is a storage register made up of D flipflops. It is not a shift register.
• For parallel In data, Number of clock pulse needed are equal to 1.
• For parallel Out data, Number of Clock pulse needed are equal to 0.
SIPO-Serial In Parallel Out shift register
Figure-3 depicts SIPO shift register type.
• For 'n' bit serial input data which need to be stored, the number of clock pulse required are equal to 'n'.
• FOr 'n' bit parallel output data which need to be stored, the number of clock pulse required is zero. As no clock pulse are required for this operation.
PISO-Parallel In Serial Out shift register
Figure-4 depicts PISO shift register type.
• It is parallel data storage register. TO store 'n' bit; number of clock pulse required is equal to 1.
• To provide serial data as output, number of clock pulse needed are equal to '(n-1)'.
what is difference between
difference between FDM and OFDM
Difference between SC-FDMA and OFDM
Difference between SISO and MIMO
Difference between TDD and FDD
Difference between 802.11 standards viz.11-a,11-b,11-g and 11-n
OFDM vs OFDMA
CDMA vs GSM
Bluetooth vs zigbee
Fixed wimax vs mobile