Asynchronous FIFO design | Asynchronous FIFO Verilog code
An Asynchronous FIFO Design refers to a FIFO Design where in the data values are written to the FIFO memory from one clock domain and the data values are read from a different clock domain, where in the two clock domains are Asynchronous to each other. Asynchronous FIFO's are widely used to safely pass the data from one clock domain to another clock domain. Continuous reading Asynchronous FIFO design pdf provided below which covers Asynchronous FIFO test bench written in verilog language.
The pdf covers following topics in order to design asynchronous FIFO.
• Block diagram of Asynchronous FIFO covering FIFO memory, binary and gray counter, synchronizer, empty and full logic block etc.
• Output waveforms
• Test bench written in verilog
• Logic Synthesis summary report
• Schematic of FIFO converted from verilog code