Scrambler and Descrambler VHDL source code

-- Library Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Entity Declaration
entity Scrambler is
port(clk : in std_logic; -- Processing Clock
reset : in std_logic; -- Asynchronous reset signal
load : in std_logic; -- Load signal to load the seed value into register
seed_in : in std_logic_vector(14 downto 0); -- Seed value to load into register
data_in : in std_logic; -- Input data to transmit
valid_in : in std_logic; -- Input data valid signal
data_out : out std_logic; -- Output data from the scrambler
valid_out : out std_logic -- Output valid signal
);
end Scrambler;
architecture behaviour of Scrambler is

Signal shift_reg_s : std_logic_vector(14 downto 0);
signal valid_in1 : std_logic;
signal data_in1 : std_logic;
begin

Process( clk,reset)
begin
if reset = '1' then
shift_reg_s <= (others => '0');
valid_in1 <= '0';
data_in1 <= '0';
valid_out <= '0';
data_out <= '0';
elsif clk'event and clk = '1' then
valid_in1 <= valid_in;
data_in1 <= data_in;
if load='1' then
Shift_reg_s(0) <= seed_in(14);
Shift_reg_s(1) <= seed_in(13);
Shift_reg_s(2) <= seed_in(12);
Shift_reg_s(3) <= seed_in(11);
Shift_reg_s(4) <= seed_in(10); --it loads initiation value into 15-bit register.
Shift_reg_s(5) <= seed_in(9);
Shift_reg_s(6) <= seed_in(8);
Shift_reg_s(7) <= seed_in(7);
Shift_reg_s(8) <= seed_in(6);
Shift_reg_s(9) <= seed_in(5);
Shift_reg_s(10) <= seed_in(4);
Shift_reg_s(11) <= seed_in(3);
Shift_reg_s(12) <= seed_in(2);
Shift_reg_s(13) <= seed_in(1);
Shift_reg_s(14) <= seed_in(0);
elsif valid_in = '1' then
Shift_reg_s(14) <= Shift_reg_s(13);
Shift_reg_s(13) <= Shift_reg_s(12); -- If valid input signal is high the register
Shift_reg_s(12) <= Shift_reg_s(11); -- contents are shifted by one bit and msb bit
Shift_reg_s(11) <= Shift_reg_s(10); -- is EX-OR with 14th bit and load it into 1st bit
Shift_reg_s(10) <= Shift_reg_s(9); -- position
Shift_reg_s(9) <= Shift_reg_s(8);
Shift_reg_s(8) <= Shift_reg_s(7);
Shift_reg_s(7) <= Shift_reg_s(6);
Shift_reg_s(6) <= Shift_reg_s(5);
Shift_reg_s(5) <= Shift_reg_s(4);
Shift_reg_s(4) <= Shift_reg_s(3);
Shift_reg_s(3) <= Shift_reg_s(2);
Shift_reg_s(2) <= Shift_reg_s(1);
Shift_reg_s(1) <= Shift_reg_s(0);
Shift_reg_s(0) <= Shift_reg_s(13) xor Shift_reg_s(14);
end if;
if valid_in1 = '1' then
data_out <= shift_reg_s(0) xor data_in1;
valid_out <= '1'; -- output port.
else
data_out <= '0';
valid_out <= '0';
end if;
end if;
end process;

end behaviour;