VHDL code to display character on 7 segment display from HEX Keypad
This page of VHDL source code section covers VHDL code to display character on 7 segment display with input from HEX Keypad.
7 Segment Display

VHDL code to display character on 7 segment display
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key is
Port ( col: inout std_logic_vector(3 downto 0):="0001";
row : in std_logic_vector(3 downto 0);
clk : in std_logic;
disp_sel: out std_logic_vector(3 downto 0);
ss : out std_logic_vector(6 downto 0));
end key;
architecture Behavioral of key is
begin
process(clk) is
begin
if (rising_edge(clk)) then
col<=col(2 downto 0)& col(3);
end if;
end process;
disp_sel<="1110";
process(col,row)
begin
case (col) is
when "0001" => case row is
when "0001" => ss<= "1111110";
when "0010" => ss <= "0110011";
when "0100" => ss <= "1111111";
when "1000" => ss <= "1001110";
when others=> ss <= "0000000";
end case;
when "0010" => case (row) is
when "0001" => ss <= "0110000";
when "0010" => ss <= "1011011";
when "0100" => ss <= "1111011";
when "1000" => ss <= "0111101";
when others=> ss <= "0000000";
end case;
when "0100" => case (row )is
when "0001" => ss <= "1101101";
when "0010" => ss <= "1011111";
when "0100" => ss <= "1110111";
when "1000" => ss <= "1001111";
when others=> ss <= "0000000";
end case;
when "1000" => case (row)is
when "0001" => ss <= "1111001";
when "0010" => ss <= "1110000";
when "0100" => ss <= "0011111";
when "1000" => ss <= "1000111";
when others=> ss <= "0000000";
end case;
when others=> null;
end case;
end process;
end Behavioral;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key is
Port ( col: inout std_logic_vector(3 downto 0):="0001";
row : in std_logic_vector(3 downto 0);
clk : in std_logic;
disp_sel: out std_logic_vector(3 downto 0);
ss : out std_logic_vector(6 downto 0));
end key;
architecture Behavioral of key is
begin
process(clk) is
begin
if (rising_edge(clk)) then
col<=col(2 downto 0)& col(3);
end if;
end process;
disp_sel<="1110";
process(col,row)
begin
case (col) is
when "0001" => case row is
when "0001" => ss<= "1111110";
when "0010" => ss <= "0110011";
when "0100" => ss <= "1111111";
when "1000" => ss <= "1001110";
when others=> ss <= "0000000";
end case;
when "0010" => case (row) is
when "0001" => ss <= "0110000";
when "0010" => ss <= "1011011";
when "0100" => ss <= "1111011";
when "1000" => ss <= "0111101";
when others=> ss <= "0000000";
end case;
when "0100" => case (row )is
when "0001" => ss <= "1101101";
when "0010" => ss <= "1011111";
when "0100" => ss <= "1110111";
when "1000" => ss <= "1001111";
when others=> ss <= "0000000";
end case;
when "1000" => case (row)is
when "0001" => ss <= "1111001";
when "0010" => ss <= "1110000";
when "0100" => ss <= "0011111";
when "1000" => ss <= "1000111";
when others=> ss <= "0000000";
end case;
when others=> null;
end case;
end process;
end Behavioral;
USEFUL LINKS to VHDL CODES
Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4X1 MUX
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial
USEFUL LINKS to Verilog Codes
Following are the links to useful Verilog codes.
Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates
RF and Wireless tutorials
WLAN 802.11ac 802.11ad wimax Zigbee z-wave GSM LTE UMTS Bluetooth UWB IoT satellite Antenna RADAR