Source-Code » Full Adder Verilog HDL Code

Full Adder Verilog HDL Code

verilog hdl full adder digital logic hardware design

This page provides the Verilog HDL code for a full adder.

Full Adder Symbol

Image alt: Full Adder Symbol

Truth Table

The truth table below illustrates the behavior of a full adder:

Input-aInput-bInput-cinOutput-SUMOutput-Cout
00000
00110
01010
01101
10010
10101
11001
11111

Full Adder Verilog Code

module fulladder (
    input a, b, c,
    output s, cout
);

    assign s = a ^ b ^ c;
    assign cout = (a & b) | (a & c) | (b & c); // Corrected Cout assignment
endmodule

Explanation:

  • The module fulladder takes three inputs: a, b, and c (carry-in).
  • It produces two outputs: s (sum) and cout (carry-out).
  • The assign statements define the combinational logic.
  • The sum s is calculated as the XOR of the three inputs.
  • The carry-out cout is (a & b) | (a & c) | (b & c). This is corrected for a standard Cout assignment.

Simulation Result

Full Adder Simulation Result

Image alt: Full Adder Simulation Result