All logic gates HDL Verilog Code

This page of verilog sourcecode covers HDL code for all the logic gates using verilog.

Truth table with symbols

Verilog code

module allgate ( a, b, y ); 

input a,b; 

output [1:6] y; 

assign y[1]= a & b; 

assign y[2]= a | b, 

assign y[3]= ~a , 

assign y[4]= ~(a & b), 

assign y[5]= ~(a | b), 

assign y[6]= a ^ b; 

end module  

• After the program is synthesized create a Test bench, load the input.
• Highlight the tbw file and click onto Modelsim Simulate behavioral model.
• Now click the waveform and zoom it to view the result.

Simulation result

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