What is JESD204B interface | JESD204B tutorial
This JESD204B tutorial covers JESD204B interface basics. It mentions features of JESD204B interface, protocol layers of JESD204B interface etc.
Introduction:
The JESD204 has been introduced several years ago in 2006.
The latest revisions have made it popular over its predecessors (LVDS and CMOS)
in terms of size, cost and speed.
It is the interface between ADCs/DACs and FPGAs.
It can also be used with ASICs.
The figure-1 below depicts JESD interface used between converters and FPGA/ASIC. The standard defines multi-gigabit serial data link between converters and a receiver (e.g. FPGA or ASIC). Initially single serial lane between a converter or multiple converters and a receiver has been defined.
Latest wireless technologies LTE, LTE Advanced and 5G require implementation of DSP blocks on FPGAs or SoCs. These devices drive antenna arrays to produce multiple beams for each individual subscriber handsets. Here hundreds of megabytes of data per second are transferred between FPGAs and data converters in both transmit mode and receive mode. In this application JESD204 is ideal interface. The other applications include SDRs (Software Defined Radios), Medical Imaging Systems, Radar and Secure Communications etc.
The figure-2 depicts JESD204A interface. Following features are supported by JESD204A.
• maximum lane rate : 3.125 Gbps
• Support for multiple lanes
• Support for lane synchronization
• Support for multidevice synchronization
The figure-3 depicts JESD204B interface. Following features are supported by JESD204B.
• maximum lane rate : 12.5 Gbps
• Support for multiple lanes, lane synchronization,
multidevice synchronization
• Support for deterministic latency
• Support for harmonic clocking
JESD204B protocol stack
The figure-4 depicts JESD204B protocol stack.
It consists of PHY layer, Data link layer, Scrambling layer, Transport layer and
Application Layer.
➨Physical layer : Serializer/Deserializer (SERDES) layer
responsible for transmit/receive of characters at line rate speeds.
Includes drivers, receivers, clock and data recovery, etc.
➨Data link layer : Encoding/Decoding of optionally scrambled octets to/from
10 bit characters. It handles special control character generation /detection for
lane alignment monitoring and maintenance.
➨Scrambling layer : Optional scrambling/de-scrambling of octets to reduce EMI effects by spreading spectral peaks.
➨Transport layer: Maps conversion samples to/from framed, non-scrambled octets
➨Application layer: It takes care of various applications at transmit and
receive ends.
➨Refer difference between JESD204C and JESD204B >> versions.
Difference between JESD204 and other interface types
JESD204A vs JESD204B
LVDS vs JESD204B
Difference between 1 wire and 2 wire interface types
SPI Interface
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Difference between SPI and I2C
Difference between RS232 and RS485
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CAN vs TTCAN
CAN vs TTP
RS232 vs RS422 vs RS485 interface
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Difference between MOST25,MOST50,MOST150