Relay to FPGA interface VHDL source code

This page of VHDL source code covers Relay to FPGA interface vhdl code.

VHDL Code

Library ieee; 
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity relay1 is
Port (sw : in std_logic;
Rl1,led : out std_logic);
End realy1;

Architecture behavioral of relay1 is
Begin
Rl1 <= ws;
Led <= sw;
End behavioral;

XC2S100TQ144-5

Connector Device Pin Property
P18/3 1 Sw
P18/5 5 Rl1
P18/21 23 Led

USEFUL LINKS to VHDL CODES

Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4X1 MUX
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial

RF and Wireless tutorials

WLAN  802.11ac  802.11ad  wimax  Zigbee  z-wave  GSM  LTE  UMTS  Bluetooth  UWB  IoT  satellite  Antenna  RADAR