Relay to FPGA interface VHDL source code
This page of VHDL source code covers Relay to FPGA interface vhdl code.
VHDL Code
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity relay1 is
Port (sw : in std_logic;
Rl1,led : out std_logic);
End realy1;
Architecture behavioral of relay1 is
Begin
Rl1 <= ws;
Led <= sw;
End behavioral;
XC2S100TQ144-5
Connector | Device Pin | Property |
---|---|---|
P18/3 | 1 | Sw |
P18/5 | 5 | Rl1 |
P18/21 | 23 | Led |
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