Binary to Gray Conversion VHDL source code
This page of VHDL source code covers Binary to Gray Conversion vhdl code.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BinarytoGray is
port( b: in std_logic_vector(3 downto 0); --binary
g: out std_logic_vector(3 downto 0)); --gray
end BinarytoGray;
architecture behavioral of BinarytoGray is
begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(2) xor g(1);
b(0)<= g(1) xor g(0);
end behavioral;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BinarytoGray is
port( b: in std_logic_vector(3 downto 0); --binary
g: out std_logic_vector(3 downto 0)); --gray
end BinarytoGray;
architecture behavioral of BinarytoGray is
begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(2) xor g(1);
b(0)<= g(1) xor g(0);
end behavioral;
USEFUL LINKS to VHDL CODES
Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4X1 MUX
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial
RF and Wireless tutorials
WLAN 802.11ac 802.11ad wimax Zigbee z-wave GSM LTE UMTS Bluetooth UWB IoT satellite Antenna RADAR