N-stage Johnson counter VHDL code | Johnson counter applications

This page mentions n-stage Johnson counter vhdl code. It describes combinational logic diagram of n-stage Johnson Counter writtern with vhdl code. It mentions applications of Johnson counter.

There are two types of ring counter viz. Straight ring counter and Johnson counter.

The figure-1 depicts 5-bit Johnson counter with terminal count output "tc". This output becomes "HIGH" in last counting state "00001" before returning to state "00000".

There is no logic between output of one flip-flop and input of another flip-flop. Hence Johnson counters are very fast in operation. Maximum operating frequency of Johnson counter is expressed as follows.
fmax = 1/( t_P(max)(FF) + t_su(FF) )
Where,
t_P(max)(FF) is maximum propagation delay of flipflop output w.r.t. active clock edge.
t_su(FF) is setup time of flipflops

Johnson Counter Applications

The Johnson counter applications are as follows.
• 5-stage Johnson counter is used as decade frequency divider.
• It is used as multiphase clock signal generator.
• They are used as high accuracy clocks.
• They produce glitch free symmetric outputs/count cycle.
• They are used to drive stepper motors.

n-stage Johnson counter VHDL code

library ieee ;
use ieee.std_logic_1164.all;

-- Tbe port description of the Johnson counter
entity johnson_counter is
generic (n : integer := 5);
port ( clk : in std_logic ;
areset : in std_logic ;
count : out std_logic_vector (0 to n -1) ;
tc : out std_logic
);
end entity johnson_counter ;

architecture rtl of johnson_counter is
-- Internal counter signal
signal count_int : std_logic_vector (0 to n -1) ;
begin

-- The Johnson counter itself
process (clk , areset ) is
begin
-- The reset is active high
if areset = '1' then
-- Set all counter bits to 0, nice VHDL trick
count_int <= ( others => '0');
elsif rising_edge ( clk ) then
-- Shift the lot a stage and feed back the last one
count_int <= not count_int (n -1) & count_int (0 to n -2) ;
end if;
end process ;

-- The outputs
count <= count_int ;
-- tc high when counter is ...01 , where the dots should be all zeros.
-- tc <= ( not count_int (n -1) ) nor count_int (n -2) ;
-- tc <= '1' when count_int (n -1) = '1' and count_int (n -2) = '0' else '0';
tc <= '1' when count_int (n -2 to n -1) = "01" else '0';

end architecture rtl ;

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N-stage Johnson counter VHDL code | Johnson counter applications

Johnson Counter Applications

n-stage Johnson counter VHDL code

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