D Latch VHDL source code

This page of VHDL source code covers D Latch vhdl code.

VHDL Code

entity mydlatch1 is port (

signal d, g: in std_logic;

signal q: out std_logic

);

end mydlatch1;



architecture behavior of mydlatch1 is

-- rising edge triggered DFF

state: process (g, d)

if (g = '1') then

q < = d;

end if;

end process;

end behavior;

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