RF Wireless World

Home of RF and Wireless Vendors and Resources

One Stop For Your RF and Wireless Need

Carry Select Adder vhdl code | Carry Skip Adder vhdl code

This page describes Carry Select Adder and Carry Skip Adder combinational logic diagram. It mentions Carry Select Adder vhdl code and Carry Skip Adder vhdl code.

There are several types of adders as mentioned below.
• Ripple Carry Adder or Carry Propagate Adder
• Carry Skip Adder
• Manchester Chain Adder
• Carry Select Adder
• Carry Save Adder
• Pipelined Parallel Adder

Both carry select adder and carry skip adder are parallel adders. These adders compute addition of variable binary strings which are same or different in sizes.

It is constructed by cascading full adders in series. One full adder does addition of two binary digits at any stage. The carryout of one stage is fed to carry-in of next stage directly. Figure depicts 4 bit ripple carry adder. It is composed of 4 full adders. Bits are added as per their binary position. Each bit addition produces sum and carry. The carry out is transmitted to carry-in of next higher order bits. The final result is sum of 4 bits plus a carry out (i.e. c4).

Carry skip adder consists of simple ripple carry adder with special speed up carry chain known as skip chain. As we know from above, addition of two binary digits at any stage "i" depends on carry in "Ci", which is actually carry out Ci-1 of previous stage. To calculate sum and carry out Ci+1 of stage i, carry in (Ci) should be known in advance. In certain cases, Ci+1 can be derived without the knowledge of Ci. This block carry select adder does two operations viz. first it computes results in parallel and second selects the correct result with single stage or multiple stage methods. It increases area to enhance its speed performance. The carry select adders calculate sum and carry bits for two alternatives viz. input carry "0" and input carry "1". Once carry-in is taken, the correct computation is chosen in order to generate the desired output. Here sum is correctly outputed as soon as carry-in is available and does not wait for the carry-in to calculate the sum. Hence time taken to compute sum is avoided which gives great improvement in speed performance. Figure-2 depicts implementation of an 8 bits carry-select adder with 4-bit sections.

Carry Select Adder VHDL code

The carry select adder can be coded in VHDL as mentioned below. It has 4 components "carry_select4". Each of these use two components "ripple_carry4".

ripple_carry4

library IEEE;
use ieee.std_logic_1164.all;
entity ripple_carry4 is
port( e, f : in std_logic_vector( 3 downto 0);
carry_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
carry_out : out std_logic);
end ripple_carry4;
architecture RTL of ripple_carry4 is
begin
process(e, f, carry_in)
variable tempC : std_logic_vector( 4 downto 0 );
variable P : std_logic_vector( 3 downto 0 );
variable G : std_logic_vector( 3 downto 0 );
begin
tempC(0) := carry_in;
for i in 0 to 3 loop
P(i):=e(i) xor f(i);
G(i):=e(i) and f(i);
S(i)<= P(i) xor tempC(i);
tempC(i+1):=G(i) or (tempC(i) and P(i));
end loop;
carry_out <= tempC(4);
end process;
end;

carry_select4

library IEEE;
use ieee.std_logic_1164.all;
entity carry_select4 is
port( c, d : in std_logic_vector( 3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector( 3 downto 0);
C_output : out std_logic);
end carry_select4;
architecture RTL of carry_select4 is
component ripple_carry4
port( e, f : in std_logic_vector( 3 downto 0);
carry_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
carry_out : out std_logic);
end component;

For S0: ripple_carry4 Use entity work.ripple_carry4(RTL);
For S1: ripple_carry4 Use entity work.ripple_carry4(RTL);
signal SUM0, SUM1 : std_logic_vector( 3 downto 0 );
signal carry0, carry1 : std_logic;
signal zero, one : std_logic;
begin
zero<='0';
one<='1';
S0: ripple_carry4 port map( e=>c, f=>d, carry_in=>zero, S=>SUM0, carry_out=>carry0 );
S1: ripple_carry4 port map( e=>c, f=>d, carry_in=>one, S=>SUM1, carry_out=>carry1 );
Result<=SUM0 when C_input='0' else
SUM1 when C_input='1' else
"ZZZZ";
C_output<= (C_input and carry1) or carry0;
end;

carry_select16

library IEEE;
use ieee.std_logic_1164.all;
entity carry_select16 is

port( A, B : in std_logic_vector( 15 downto 0);
C_in : in std_logic;
SUM : out std_logic_vector( 15 downto 0);
C_out : out std_logic);
end carry_select16;
architecture RTL of carry_select16 is
component carry_select4
port( c, d : in std_logic_vector( 3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector( 3 downto 0);
C_output : out std_logic);
end component;

For S0: carry_select4 Use entity work.carry_select4(RTL);
For S1: carry_select4 Use entity work.carry_select4(RTL);
For S2: carry_select4 Use entity work.carry_select4(RTL);
For S3: carry_select4 Use entity work.carry_select4(RTL);
signal tempc1, tempc2, tempc3 : std_logic;
begin
S0: carry_select4 port map( c=>A ( 3 downto 0 ), d =>B ( 3 downto 0 ), C_input=>C_in, Result=>SUM ( 3 downto 0 ), C_output=>tempc1 );
S1: carry_select4 port map( c=>A ( 7 downto 4 ), d =>B ( 7 downto 4 ), C_input=>tempc1, Result=>SUM ( 7 downto 4 ), C_output=>tempc2 );
S2: carry_select4 port map( c=>A ( 11 downto 8 ), d =>B ( 11 downto 8 ), C_input=>tempc2, Result=>SUM ( 11 downto 8 ), C_output=>tempc3 );
S3: carry_select4 port map( c=>A ( 15 downto 12 ), d =>B ( 15 downto 12 ), C_input=>tempc3, Result=>SUM ( 15 downto 12 ), C_output=>C_out );
end;

USEFUL LINKS to VHDL CODES

Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop