Mealy Machine Verilog Code | Moore Machine Verilog Code
This page covers Mealy Machine Verilog Code and Moore Machine Verilog Code.
Mealy Machine Verilog code
Following is the figure and verilog code of Mealy Machine.
module mealy_verilog_code(out, in, rst, clk);
output out;
input in;
input clk, rst;
reg out;
reg[1:0] state;
parameters0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: if(in==0) begin out=0; state=s1; end
else begin out=0; state=s0; end
s1: if(in==0) beginout=0; state=s1; end
else begin out=0; state=s2; end
s2: if(in==0) begin out=0; state=s3; end
else begin out=0; state=s0; end
s3: if(in==0) begin out=0; state=s1; end
else begin out=1; state=s2; end
default: state=s0;
endcase
end
endmodule
output out;
input in;
input clk, rst;
reg out;
reg[1:0] state;
parameters0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: if(in==0) begin out=0; state=s1; end
else begin out=0; state=s0; end
s1: if(in==0) beginout=0; state=s1; end
else begin out=0; state=s2; end
s2: if(in==0) begin out=0; state=s3; end
else begin out=0; state=s0; end
s3: if(in==0) begin out=0; state=s1; end
else begin out=1; state=s2; end
default: state=s0;
endcase
end
endmodule
Moore Machine Verilog code
Following is the figure and verilog code of Moore Machine.
module moore_verilog_code(out, in, rst, clk);
output out;
input in;
input clk, rst;
reg out;
reg[1:0] state;
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: begin out=0; if(in==0) state=s1; else state=s0; end
s1: begin out=0; if(in==0) state=s1; else state=s2; end
s2: begin out=0; if(in==0) state=s3; else state=s0; end
s3: begin out=1; if(in==0) state=s1; else state=s2; end
default: state=s0;
endcase
end
endmodule
output out;
input in;
input clk, rst;
reg out;
reg[1:0] state;
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: begin out=0; if(in==0) state=s1; else state=s0; end
s1: begin out=0; if(in==0) state=s1; else state=s2; end
s2: begin out=0; if(in==0) state=s3; else state=s0; end
s3: begin out=1; if(in==0) state=s1; else state=s2; end
default: state=s0;
endcase
end
endmodule
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